Yes, but there’s no way I could distill all my VLSI classes into a few sentences here.

A few are:

a) shore space on the chip is limited, you can’t go off chip for everything

b) taping out multiple chips is expensive

c) increasing the number of dies you package together reduces yield (Intel GPU Max)

d) if the distance is very short it will be much faster to stay on chip than to go over a phy and then the substrate. So it depends on what you’re doing which solution is better. Also as process nodes hav…

I can't even read the transcript, YOU KNOW. Comes up 35 times.