I am writing and releasing my two-part series on Cerebras, Cerebranalysis, on the two days leading up to the IPO! Today’s article is part 1 and focuses on the science and technology behind the Cerebras Dinner Plate (wafer-scale engine).

I discuss their compiler complexity and inefficiency, how Cerebras claims a 100% yield rate on their wafer-scale engines, why PVT (process, voltage, temperature) calibration is one of Cerebras’s most important innovations, the science behind the one mechanism which enables their 15x inference speedup: pipeline parallelism, and the two key constraints their architecture has, first being severe memory constraints and second being the limited I/O bandwidth.

We go one step beyond most other technical research out there. We underline why all this technological analysis is economically relevant for their product. I will walk you through the single conclusion that follows from our research, which forms the foundational premise for all of our economic and business-related analysis coming tomorrow.