> And the waves solve wetware-specific problems, like conduction delay (silicon chips operate at the speed of light) and synchronization (computers have internal clocks, or can synchronize with atomic clocks via the Internet).
Silicon chips definitely deal with conduction delay. The speed of light is very fast, but at 4 GHz electric signals (moving at roughly 2/3 the speed of light) can only travel 5 cm in one clock cycle. Traveling 1 cm uses 20% of the cycle, etc. Computers also have to deal with various types of synchronization issues for a variety of reasons.
However, the logic here was flawed from the start, because artificial neural networks are a mathematical model simulated on a computer and the properties of the computational substrate of a simulation don't carry through into the simulation. And so ANNs indeed do not have to deal with conduction delays and synchronization issues the same way that biological neural networks do, but the reason does not have anything to do with the low-level details of silicon chips.
In an ANN, there is simply a list of neurons, a record of which neurons are connected to which others, and an assignment of weights to these connections. There is normally not an assignment of lengths to the connections. Therefore there can be no conduction delay, for example. You could create a nonstandard ANN with lengths and simulated conduction delays if you wanted, as that freedom is the nature of simulation. The conduction delays in the wires within the silicon chip don't inherently create conduction delays in the ANN, because the connections in the ANN are not wires in the ANN, they are numerical data upon which the silicon chip performs calculations. Just like the flatness of the silicon chip doesn't prevent simulated 3D environments, etc.
This may seem piddly, but it's important to keep in mind that the properties of an ANN come from the properties of the mathematical model, not from the properties of wiring in silicon chips.
> And the waves solve wetware-specific problems, like conduction delay (silicon chips operate at the speed of light) and synchronization (computers have internal clocks, or can synchronize with atomic clocks via the Internet).
Silicon chips definitely deal with conduction delay. The speed of light is very fast, but at 4 GHz electric signals (moving at roughly 2/3 the speed of light) can only travel 5 cm in one clock cycle. Traveling 1 cm uses 20% of the cycle, etc. Computers also have to deal with various types of synchronization issues for a variety of reasons.
However, the logic here was flawed from the start, because artificial neural networks are a mathematical model simulated on a computer and the properties of the computational substrate of a simulation don't carry through into the simulation. And so ANNs indeed do not have to deal with conduction delays and synchronization issues the same way that biological neural networks do, but the reason does not have anything to do with the low-level details of silicon chips.
In an ANN, there is simply a list of neurons, a record of which neurons are connected to which others, and an assignment of weights to these connections. There is normally not an assignment of lengths to the connections. Therefore there can be no conduction delay, for example. You could create a nonstandard ANN with lengths and simulated conduction delays if you wanted, as that freedom is the nature of simulation. The conduction delays in the wires within the silicon chip don't inherently create conduction delays in the ANN, because the connections in the ANN are not wires in the ANN, they are numerical data upon which the silicon chip performs calculations. Just like the flatness of the silicon chip doesn't prevent simulated 3D environments, etc.
This may seem piddly, but it's important to keep in mind that the properties of an ANN come from the properties of the mathematical model, not from the properties of wiring in silicon chips.